This invention relates to optical devices and, more particularly to integration of active optical devices with other components.
Top side emitting/processed devices are ones in which the optical devices are oriented away from the substrate of the wafer on which the devices were formed (i.e. containing the optical devices). Bottom (or back) side emitting/processed devices have the optical devices themselves oriented towards the substrate.
Top side emitting/receiving devices are the common device configuration used by industry and so are more readily available, more easily obtained, and more widely understood and characterized.
Moreover, top side emitting lasers, receiving detectors, or reflective or absorbative modulators can be easily made to operate at wavelengths at which the substrate for the optical devices is opaque, since in these types of devices light does not need to travel through the substrate.
In addition, top side emitting/receiving/processed devices are easier to test than bottom side devices, before integration with electronics, since contacts and optical access are on the same side (top) of the wafer.
The driver and control circuitry for these devices is most commonly fabricated from silicon circuits. The electrical contacts are also on the front (i.e. top) surface of the driver and control circuitry silicon wafer. Where the electrical contacts of top side of the optical devices and driver and control circuitry chip, it is difficult to connect them together. Inverting the top side optical devices would allow electrical interconnection to the driver and control circuitry but prevents correct optical functionality, absent a hole being made in the electronic driver chip.
Others have attempted other ways of integrating of top emitting devices with electronics. One approach to doing so is shown in FIG. 1. In the process of FIG. 1, the process starts with a wafer 100. One or more isolation holes, grooves or trenches 102 are made in the epitaxial layers 104 and contacts 106, 108 are formed on the top surface 110. A superstrate 112 is attached to the upper surface 110 for strength. The substrate 114 of the wafer 100 is then completely removed. The optical devices are then defined in the epitaxial layers 104. Vias or other openings 116 are then made from the bottom (also called the xe2x80x9cbackxe2x80x9d) side 118 through the epitaxial layers 104 to the underside contacts 106, 108. After an insulator (not shown) has been applied to the vias 116 as necessary to ensure an electrical short does not occur, conductors 120, 122 are formed on the side of the vias 116 so as to, in effect, provide an ability to connect to the electrical contacts 106, 108 on the bottom side 118 via the conductors 120, 122 and contacts 124, 126 formed on the bottom side 118. Solder can then be applied for connection of the top emitting device to other electrical contacts 130, for example, on a circuit board 132 or another wafer.
The complexity of this approach, the difficulty in attaching a superstrate and keeping that superstrate robust over operational temperature cycling, and difficulty in achieving reasonable yields, make this approach undesirable for commercial application.
Thus, there is a need for a process that can make top side optical devices that can be integrated with electronics that does not suffer form the above problems.
While, to avoid the thermal problems of the prior art associated with the superstrate, one might consider adapting the prior art approach by an analogous approach of not using a superstrate and etching through the substrate, such as shown in FIG. 2.
In the process of FIG. 2, a wafer 200 is etched and doped to form the optical device 202. Contacts 204, 206 are formed on the device. The substrate 208 is thinned to allow for the etching of vias. Vias 210 are then etched through the substrate 208 until the contacts 204, 206 on the top of the device are reached. A dielectric (not shown) coating is made on the via wall and a conductor material is added into the hole, on top of the dielectric, to form a contacts 212, 214 extending from the back side to the contacts 204, 206 on top. Solder or some other electrically connective material 216 can then be added to the contacts for joining the device to another device.
However, while the process of FIG. 2 addresses the problems of the prior art, particularly those caused by the superstrate, that process does not remedy the other problems in the prior art. For example, alignment between the features on the two sides of the wafer must still be properly carried out, so there is still a risk of damage to the optical devices, particular as densities of devices per chip increase.
Thus, we have developed a fabrication technique for creating top emitting/receiving/modulating structures, such as VCSELS, detectors or modulators, that can be closely integrated with electronic circuits. It allows alignment-dependent processing to occur only on the top side of the optical devices, thus reducing, if not eliminating, the need for backside alignment processing in which precision elements on two sides of a wafer have to be aligned relative to each other.
Since new VCSEL developments are first implemented in top-emitting devices, our approach allows use of the newest technologies, for example, the present 1310 micron or 1500 micron wavelength VCSELs.
In addition, through use of the teachings of the invention, costs are lowered because, instead of having to fabricate special purpose devices, the devices can be procured from multiple vendors as xe2x80x9coff-the-shelfxe2x80x9d items.
Our approach can also result in improved product lifetimes and overall yields since industry standard semiconductor processing techniques are used in the individual fabrication steps.
By employing the teachings of the invention, a higher density of interconnects is possible. As a result, in some implementations, the invention allows for close interconnect spacing, for example as close as a 20 micron pitch in current technologies and smaller in the future.
In addition, by forming interconnections through the substrate, interconnection points are not limited to the periphery of the chip. The entire otherwise unused surface is available for potential interconnections.
By employing the teachings of the invention, more direct interconnects between driver circuits and optical devices can be made. This lowers the resistance, capacitance and inductance of the interconnect. As a result, parasitics are reduced, making for lower power and drive requirements and increased device speed.
In addition, manufacturability is improved because the interconnects can be fabricated when the optical device is either in die or wafer form. Moreover, in either case, the interconnects can be fabricated in the die or wafer all at once. Alternatively, in alternative variants, a similar technique can be used where both the optical devices and electronic chips are individual dies, where the optical devices are on dies and will be connected onto a driver circuit wafer, or where the optical devices and driver circuits are still both in wafer form.
A further advantage is that the vias, that are used to form the connections, can be fabricated during optical device manufacturing. In addition, substrate removal is simple and the process does not require additional processing once the substrate removal occurs.
A further advantage is that the process can be straightforwardly used for integration of different combinations of acoustic, thermal, optical, mechanical sensors, and active devices together or for combining two, three or more devices/wafers/chips together.
A further advantage achievable by employing the teachings of the invention is better thermal management of top-emitting VCSELs because they are heat sinked to the driver and control circuitry.
A still further advantage achievable by employing the teachings of the invention is that incorporation of an optical coupler, face plate, MEMS detectors, optical combiners, optical splitters, lens, micro lenses or other optical or electrical devices can be accommodated during the fabrication process.
It should be understood that a further advantage of the invention is its applicability to both light-emitting and light-detecting devices.
The advantages and features described herein are a few of the many advantages and features available from representative embodiments and are presented only to assist in understanding the invention. It should be understood that they are not to be considered limitations on the invention as defined by the claims, or limitations on equivalents to the claims. For instance, some of these advantages are mutually contradictory, in that they cannot be simultaneously present in a single embodiment. Similarly, some advantages are applicable to one aspect of the invention, and inapplicable to others. Thus, this summary of features and advantages should not be considered dispositive in determining equivalence. Additional features and advantages of the invention will become apparent in the following description, from the drawings, and from the claims.